1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a three-dimensional (3D) MOSFET employing a hard mask spacer.
2. Description of the Related Art
A semiconductor device has discrete devices, such as a MOS transistor, employed as a switching device. As the semiconductor device becomes more integrated, the MOS transistor becomes scaled down. Consequently, a short channel effect is generated because a channel length of the MOS transistor is reduced.
In general, a method of doping channel ions in high concentration into a channel region is used to prevent a reduction of a threshold voltage due to the short channel effect. However, when the channel ions are doped at a high concentration, channel resistance increases to reduce a current driving capability.
Therefore, to reduce the short channel effect, research has been made into a three-dimensional field effect transistor. In particular, research on a Fin field effect transistor with which perfect depletion may be obtained due to the narrow channel width has been made.
The method of fabricating the three-dimensional field effect transistor was disclosed in U.S. Patent Laid-Open No. 2003/0,141,546(A1) by Maegawa, entitled “MOS semiconductor and Method of manufacturing the same”.
FIGS. 1 to 6 are cross-sectional views illustrating methods of fabricating the three-dimensional field effect transistor disclosed in the U.S. Patent Laid-Open No. 2003/0,141,546(A1).
Referring to FIG. 1, a semiconductor substrate 1 is prepared. A substrate oxide layer 6 is formed on a main surface of the semiconductor substrate 1 by a thermal oxidation process at 1000° C. Further, a mask nitride layer 7 is formed on the substrate oxide layer 6.
Referring to FIG. 2, the substrate oxide layer 6 and the mask nitride layer 7 are patterned to have a flat shape of semiconductor layer 13 including a channel region and source and drain regions.
Next, the main surface of the semiconductor substrate 1 is selectively etched using the patterned substrate oxide layer 6 and mask nitride layer 7 as an etch mask. Consequently, the main surface is selectively recessed. In particular, a trench is formed around the semiconductor layer 13.
Here, pattern shapes of the substrate oxide layer 6 and the mask nitride layer 7 are determined to have a width, which corresponds to a channel width in the semiconductor layer 13, less than or equal to twice the maximum channel depletion layer.
Referring to FIG. 3, an oxide layer, which is to be an isolation layer 2, is deposited on the semiconductor substrate 1 by HDP-CVP to cover the semiconductor layer 13. Next, the isolation layer 2 is removed by a chemical mechanical polishing (CMP) method until an upper surface of the mask nitride layer 7 is exposed.
Referring to FIG. 4, a resist pattern (not shown) is formed on the semiconductor substrate 1 having the isolation layer 2. Subsequently, selective etching is performed using the resist pattern as an etch mask. As a result, the upper surface of the isolation layer 2 is recessed downward in the regions adjacent to a pair of sidewalls of some regions of the semiconductor layer 13, which is to be the channel region.
Referring to FIG. 5, the mask nitride layer 7 and the substrate oxide layer 6 are removed by etching with a phosphoric acid (H3PO4) solution and a hydrofluoric acid (HF) solution.
Referring to FIG. 6, a gate insulating layer 3 is formed on the entire surface of the intermediate structure obtained after the step of FIG. 5, by a thermal oxidation process. As a result, the pair of sidewalls and the upper surface of some regions of the semiconductor layer 13 to be the channel region 5 are covered by the gate insulating layer 3. Next, a polysilicon layer, which is to be a gate electrode 4, is deposited. Next, the polysilicon layer is patterned to have a predetermined pattern by photolithography and plasma processes. As a result, the gate electrode 4 is formed.
According to the method disclosed in the U.S. Patent Laid-Open No. 2003/0,141,546(A1), the sidewalls as well as the upper surface of the channel region 5 are covered by the gate electrode 4. Further, the channel region 5 may be formed to have a width less than or equal to twice that of the maximum depletion layer. Therefore, according to the above method, it is possible to improve the short channel effect.
However, as illustrated with reference to FIG. 5, in the above method, the isolation layer adjacent to the sidewalls of some regions of the semiconductor layer 13 is recessed, and then the mask nitride layer 7 is removed. Here, the mask nitride layer 7 is removed with a phosphoric acid solution. However, while removing the mask nitride layer, the semiconductor layer 13 may be damaged by the phosphoric acid solution. In particular, when the semiconductor layer 13 has a width less than or equal to twice that of the maximum depletion layer, the damage of the semiconductor layer 13 may lead to a fatal defect in transistor operation.
Further, before the isolation layer 2 is deposited, a trench oxide layer and a liner may be formed on the inner wall of the trench to prevent the semiconductor layer 13 from being damaged. The liner serves to protect the trench oxide layer while the isolation layer 2 is recessed. In addition, the trench oxide layer prevents the semiconductor layer 13 from being damaged while the mask nitride layer 7 is removed. However, while the isolation layer 2 is recessed, the liner may be damaged, and the trench oxide layer may also be damaged. As a result, while the mask nitride layer 7 is removed with the phosphoric acid solution, the semiconductor layer 13 may be damaged. Consequently, while the isolation layer 2 is recessed, it is necessary to prevent the liner from being damaged.